One of the most important factors in the design and operation of modern integrated electronic devices is the speed and size of semiconductor memory devices. The ability to construct high density and high-speed random access memory cells and nonvolatile memory cells is an important concern of electronic device designers.
Currently, the state of the art memory cell uses a pass gate transistor coupled to a storage capacitor. The pass gate transistor serves as a switch to access the capacitor either to charge the capacitor when information is stored in the memory cell or to determine if the capacitor has been charged as information is read from the memory cell. Both the pass gate transistor and the capacitor are constructed either in the bulk of a semiconductor substrate or in layers built upon the semiconductor substrate. A wide variety of geometries and placements of the pass gate transistor and the capacitor have been used in the past. The majority of these geometries have used pass gate transistors and capacitors which are formed horizontally with respect to the substrate surface. This orientation of the devices inherently uses a great deal of surface area and therefore increases the necessary size of a memory array.
In addition, there have been prior attempts to use ferroelectric capacitors to form nonvolatile memory devices. Such nonvolatile memory devices comprise a capacitor using a ferroelectric material in its storage layer, and a pass gate transistor to access the ferroelectric capacitor. The nonvolatile devices have also been constructed in a primarily horizontal orientation and have thus suffered similar limitations in the resulting device size.
Therefore, a need has arisen for a memory cell geometry which achieves the maximum device density and is usable in the dynamic and nonvolatile memory applications.